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ZL30414 SONET/SDH Clock Multiplier PLL
Data Sheet Features
* Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 622.08 MHz Provides a CML differential clock at 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Lock Indicator Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supply Ordering Information ZL30414QGC 64 Pin TQFP
July 2003
* * * * * * * *
-40C to +85C
Description
The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates. The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. The ZL30414 provides a LOCK indication.
Applications
* * SONET/SDH line cards Network Element timing cards
LPF
C622oEN-A C622oEN-B C622oEN-C C622oEN-D
C622oP/N-A C19i Frequency & Phase Detector Loop Filter VCO Frequency Dividers and Clock Drivers C622oP/N-B C622oP/N-C C622oP/N-D C155oP/N C19o
19.44MHz State Machine Reference and Bias Circuit
LOCK
BIAS
VDD GND VCC
C155oEN C19oEN 05
Figure 1 - Functional Block Diagram
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Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30414
Data Sheet
GND VCC1 VCC C155oN C155oP GND VCC2 LPF GND GND BIAS C155oEN C622oEN-A C622oEN-B C622oEN-C C622oEN-D
GND C622oN-A C622oP-A VCC GND C622oP-B C622oN-B VCC GND C622oN-C C622oP-C VCC GND C622oP-D C622oN-D VCC
64 2 62 60 58 56 54 52 50
48 46 44
65 - EP_GND
4 6
42 8 10 38 12 36 14 34 16 18 20 22 24 26 28 30 32
ZL30414
40
GND VCC VDD GND VCC GND VDD GND NC GND GND LOCK GND C19o VDD GND
Figure 2 - TQFP 64 pin (Top View)
Pin Description
Pin Description Table Pin # 1 2 3 4 5 6 7 8 9 10 Name GND VCC1 VCC C155oN C155oP GND VCC2 LPF GND GND Ground. 0 volt. Positive Analog Power Supply. +3.3V 10%. Positive Analog Power Supply. +3.3V 10%. C155 Clock Output (CML). These outputs provide a differential 155.52 MHz clock. Ground. 0 volt Positive Analog Power Supply. +3.3V 10% Low Pass Filter (Analog). Connect to this pin external RC network (RF and CF) for the low pass filter. Ground. 0 volt Ground. 0 volt. Description
GND VDD NC NC NC VDD IC NC NC C19oEN GND C19i VDD GND VDD GND
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ZL30414
Pin Description Table (continued) Pin # 11 12 C155oEN Name BIAS Description Bias. See Figure 12 for the recommended bias circuit.
Data Sheet
C155o Clock Enable (CMOS Input). If tied high this control pin enables the C155oP/N differential driver. Pulling this input low disables the output clock and deactivates differential drivers. C622 Clock Output Enable A (CMOS Input). If tied high this control pin enables the C622oP/N-A output clock. Pulling this input low disables the output clock without deactivating differential drivers. C622 Clock Output Enable B (CMOS Input). If tied high this control pin enables the C622oP/N-B output clock. Pulling this input low disables the output clock without deactivating differential drivers. C622 Clock Output Enable C (CMOS Input). If tied high this control pin enables the C622oP/N-C output clock.Pulling this input low disables the output clock without deactivating differential drivers. C622 Clock Output Enable D (CMOS Input). If tied high this control pin enables the C622oP/N-D output clock.Pulling this input low disables the output clock without deactivating differential drivers. Ground. 0 volt Positive Digital Power Supply. +3.3V 10% No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Positive Digital Power Supply. +3.3V 10% Internal Connection. Connect this pin to Ground (GND). No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. C19o Output Enable (CMOS Input). If tied high this control pin enables the C19o output clock. Pulling this pin low forces output driver into a high impedance state. Ground. 0 volt. C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44 MHz. Positive Digital Power Supply. +3.3V 10% Ground. 0 volt. Positive Digital Power Supply. +3.3V 10% Ground. 0 volt.
13
C622oEN-A
14
C622oEN-B
15
C622oEN-C
16 17 18 19 20 21 22 23 24 25 26
C622oEN-D GND VDD NC NC NC VDD IC NC NC C19oEN
27 28 29 30 31 32
GND C19i VDD GND VDD GND
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Pin Description Table (continued) Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Name GND VDD C19o GND LOCK GND GND NC GND VDD GND VCC GND VDD VCC GND VCC C622oN-D C622oP-D GND VCC C622oP-C C622oN-C GND VCC C622oN-B C622oP-B Ground. 0 volt Positive Digital Power Supply. +3.3V 10% Description
Data Sheet
C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS clock at 19.44 MHz. Ground. 0 volt. Lock Indicator (CMOS Output). This output goes high when PLL is frequency locked to the input reference C19i. Ground. 0 volt. Ground. 0 volt. No internal bonding Connection. Leave unconnected. Ground. 0 volt. Positive Digital Power Supply. +3.3V 10% Ground. 0 volt. Positive Analog Power Supply. +3.3V 10% Ground. 0 volt. Positive Digital Power Supply. +3.3V 10% Positive Analog Power Supply. +3.3V 10% Ground. 0 volt. Positive Analog Power Supply. +3.3V 10%. C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Positive Analog Power Supply. +3.3V 10%. C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt. Positive Analog Power Supply. +3.3V 10%. C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current.
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Pin Description Table (continued) Pin # 60 61 62 63 64 65 Name GND VCC C622oP-A C622oN-A GND NC Ground. 0 volt Positive Analog Power Supply. +3.3V 10%. Description
Data Sheet
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt No internal bonding Connection. Leave unconnected.
1.0
Functional Description
The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections.
1.1
Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit.
1.2
Lock Indicator
The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than 300 ppm apart from the input reference frequency then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds 1000 ppm.
1.3
Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown in Figure 3.
ZL30414
Frequency and Phase Detector
LPF Loop Filter RF CF RF=8.2 k, CF=470 nF
VCO
Figure 3 - Loop Filter Elements
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1.4 VCO
Data Sheet
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
1.5
Output Interface Circuit
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 622.08 MHz, one CML differential clock at 155.52 MHz and a single-ended 19.44 MHz output clock. This block provides also a 19.44MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable pin.
Output Clocks C622oP/N-A C622oP/N-B C622oP/N-C C622oP/N-D C155oP/N C19o
Output Enable Pins C622oEN-A C622oEN-B C622oEN-C C622oEN-D C155oEN C19oEN
Table 1 - Output Enable Control To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
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2.0 ZL30414 Performance
Data Sheet
The following are some of the ZL30414 performance indicators that complement results listed in the Characteristics section of this data sheet.
2.1
Input Jitter Tolerance
Jitter tolerance is a measure of the PLL's ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. The input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for OC-192, OC-48, and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
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2.2 Jitter Transfer Characteristic
Data Sheet
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer characteristic for the ZL30414 configured with recommended loop filter components (RF=8.2 k, CF=470 nF) is shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3.0V to 3.6V) and temperature (-40C to 85C) ranges.
Figure 5 - Jitter Transfer Characteristic
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Zarlink Semiconductor Inc.
ZL30414
3.0
3.1
Data Sheet
Applications
Ultra-low jitter SONET/SDH equipment clocks
The ZL30414 functionality and performance complements the entire family of the Zarlink's advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 6) .
C622oA C622oB C19i C622oC
LVPECL LVPECL LVPECL LVPECL CML CMOS
622.08 MHz 622.08 MHz 622.08 MHz 622.08 MHz 155.52 MHz 19.44 MHz
ZL30414
C622oD C155o C19o
LPF
C622oEN-C C622oEN-A C622oEN-B C622oEN-D
CF
LOCK
C155oEN
RF
C19oEN
C19o PRI SEC Synchronization Reference Clocks RefSel RefAlign C155o C34o/C44o C16o C8o C6o C4o C2o C1.5o F16o LOCK HOLDOVER F8o F0o
C20i
CMOS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
19.44 MHz 155.52 MHz 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz
ZL30407 or MT90401
PRIOR SECOR
A0 - A6
20 MHz OCXO
D0 - D7
R/W
DS
CS
Data Port
uP
Controller Port
Note: Only main functional connections are shown
Figure 6 - SONET/SDH Equipment Clock
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Data Sheet
The ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 7).
C622oA C622oB C19i C622oC
LVPECL LVPECL LVPECL LVPECL CML CMOS
622.08 MHz 622.08 MHz 622.08 MHz 622.08 MHz 155.52 MHz 19.44 MHz
ZL30414
LPF
C622oEN-B C622oEN-C
C622oD C155o C19o
C1
C2
C19oEN
R1
LOCK
C155oEN
R1 = 680 C1 = 820 nF C2 = 22 nF
C622oEN-D
C622oEN-A
C19o PRI SEC Synchronization Reference Clocks C16o C8o C6o RSEL C4o
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
19.44 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz
MT9046
LOCK HOLDOVER C20i
C2o C1.5o F16o F8o F0o
FLOCK
20 MHz TCXO
MS1 MS2 FS1 FS2
TCLR
PCCi
uC
Hardware Control
Note: Only main functional connections are shown
Figure 7 - SONET/SDH Line Card
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ZL30414
3.2 3.2.1 Recommended Interface circuit LVPECL to LVPECL Interface
Data Sheet
The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at 622.08 MHz. The LVPECL output drivers require a 50 termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver.
+3.3V
0.1uF ZL30414 VCC VCC=+3.3V LVPECL Receiver
R1 LVPECL Driver 622.08 MHz C622oN-A R2 GND C622oP-A Z=50
R1
Z=50
R2
Typical resistor values: R1 = 130, R2 =82
Figure 8 - LVPECL to LVPECL Interface
3.2.2
CML to CML Interface
The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a 50 load at the terminating end if the receiver is CML type.
+3.3V Low impedance DC bias source CML Receiver
0.1uF ZL30414 VCC
CML Driver 155.52 MHz
0.1uF C155oP
Z=50
50
50
Z=50 C155oN 0.1uF
GND
Figure 9 - CML to CML Interface
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3.2.3 CML to LVDS Interface
Data Sheet
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage) as minimum 1.125V, typical 1.2V, and maximum 1.375V. The following figure provides a recommendation for LVDS applications.
+3.3V
0.1uF ZL30414 VCC 10nF VCC=+3.3V LVDS Receiver
CML Driver 155.52 MHz
C155oP
Z=50
R1
R1
Z=50 C155oN 10nF R2 R2
100
GND
Typical resistor values: R1 = 16k, R2 = 10k
Figure 10 - LVDS Termination
3.2.4
CML to LVPECL Interface
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as close as possible to the LVPECL receiver.
+3.3V
0.1uF ZL30414 VCC VCC=+3.3V LVPECL Receiver
CML Driver 155.52 MHz
C155oP
Z=50
10nF
R1
R1
Z=50 C155oN 10nF R2 R2
GND Typical resistor values: R1 = 82, R2 =130
Figure 11 - CML to LVPECL Interface
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ZL30414
3.3 Power supply and BIAS circuit filtering recommendations
Data Sheet
Figure 12 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink's web site for updates.
0.1uF +3.3V Power Rail GND GND
0.1uF
0.1uF
0.1uF
0.1uF
GND
VCC
GND
VCC
VCC
VCC
Ferrite Bead + 0.1uF 10uF 0.1uF
GND 4.7
33uF + 0.1uF
0.1uF
64 2 46 4 6 GND 8 62 60 58 56 54 52 50 48
VCC1 VCC
GND VCC VDD
GND
44
0.1uF
VCC
VCC2
+ 33uF 0.1uF
GND
42
0.1uF
VDD
220
+ 33uF
BIAS
0.1uF
GND 10 GND
11 12
ZL30414
GND
40
0.1uF
GND GND 38 GND 36
14 34 16 18 20 22 24 26 28 30 32
VDD GND 0.1uF
GND
VDD
GND VDD
VDD
0.1uF
0.1uF
Notes: 1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same ground plane. 2. Select Ferrite Bead with IDC > 400mA and RDC in a range from 0.10 to 0.15
Figure 12 - Power Supply and BIAS circuit filtering
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Zarlink Semiconductor Inc.
GND VDD GND 0.1uF
ZL30414
4.0 Characteristics
Data Sheet
Absolute Maximum Ratings Characteristics 1 2 3 4 5 6 Supply voltage Voltage on any pin Current on any pin ESD Rating Storage temperature Package power dissipation Sym VDDR, VCCR VPIN IPIN VESD TST PPD -55 Min TBD -0.5 -0.5 Max TBD VCC + 0.5 VDD + 0.5 30 1250 125 1.8 Units V V mA V C W
Voltages are with respect to ground unless otherwise stated. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 Operating Temperature Positive Supply Sym TOP VDD, VCC Min -40 3.0 Typ 25 3.3 Max +85 3.6 Units C V Notes
Voltages are with respect to ground unless otherwise stated. Typical figures are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics Characteristics 1 Supply Current Sym IDD+ICC Min Typ 146 Max Units mA Notes LVPECL, CML drivers disabled and unterminated Note 1 Note 2
2
Incremental Supply Current to single LVPECL driver (driver enabled and terminated, see Figure 8) Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 9) CMOS: High-level input voltage CMOS: Low-level input voltage CMOS: Input leakage current
ILVPECL
37
mA
3
ICML
26
mA
Note 3
4 5 6
VIH VIL IIL
0.7VDD 0 1
VDD 0.3VDD 5
V V uA VI = VDD or 0V
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DC Electrical Characteristics (continued) Characteristics 7 CMOS: Input bias current for pulled-down inputs: C622oEN-A, C622oEN-C, C622oEN-D, OC-CLKoEN CMOS: Input bias current for pulled-up inputs: , C622oEN-B, C19oEN CMOS: High-level output voltage CMOS: Low-level output voltage LOCK pin: High-level output voltage LOCK pin: Low-level output voltage CMOS: C19o output rise time CMOS: C19o output fall time LVPECL: Differential output voltage (622.08 MHz) LVPECL: Offset voltage (622.08 MHz) LVPECL: Output rise/fall times (622.08 MHz) CML: Differential output voltage (155.52 MHz) CML: Offset voltage (155.52 MHz) CML: Output rise/fall times (155.52 MHz) Sym IB-PU Min Typ 300 Max Units uA
Data Sheet
Notes VI = VDD
8
IB-PD
90
uA
VI = 0V
9 10 11 12 13 14 15 16 17 18 19 20
VOH VOL VOH VOL TR TF IVOD_LVPECLI VOS_LVPECL TRF IVOD_CMLI VOS_CML TRF
2.4 0.4 2.4 0.4 1.8 1.1 1.17 Vcc1.31 Vcc1.20 170 0.73 Vcc0.58 Vcc0.54 220 Vcc0.50 Vcc1.09 3.3 1.4
V V
IOH = 8 mA IOL = 4 mA IOH = 0.5 mA IOL = 0.5 mA
ns ns V V ps V V ps
18 pF load 18 pF load Note 2 Note 2 Note 2 Note 3 Note 3 Note 3
-
: Voltages are with respect to ground unless otherwise stated. :Typical figures are for design aid only: not guaranteed and not subject to production testing. Supply voltage and operating temperature are as per Recommended Operating Conditions Note 1: The ILVPECL current is determined by the termination network connected to LVPECL outputs. More than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation. Note 2: LVPECL outputs terminated with ZT = 50 resistors biased to VCC-2V (see Figure 8) Note 3: CML outputs terminated with ZT = 50 resistors connected to low impedance DC bias voltage source (see Figure 9)
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AC Electrical Characteristics - Output Timing Parameters Measurement Voltage Levels Characteristics 1 Threshold Voltage Sym VT-CMOS VT-LVPECL VT-CML VHM VLM CMOS 0.5VDD LVPECL 0.5VOD_LVPECL CML
Data Sheet
Units V
0.5VOD_CML
2 3
Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low
0.7VDD 0.3VDD
0.8VOD_LVPECL 0.2VOD_LVPECL
0.8VOD_CML 0.2VOD_CML
V V
Voltages are with respect to ground unless otherwise stated.
Timing Reference Points
All Signals
VHM VT VLM tIF, tOF tIR, tOR
Figure 13 - Output Timing Parameter Measurement Voltage Levels
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ZL30414
AC Electrical Characteristics - C19i Input to C19o, C155o and C622o Output Timing Characteristics 1 2 3 4 5 C19i to C19o delay C19i to C155o delay C19i to C622oA delay C155o duty cycle C622o duty cycle Sym tC19D tc155D tC622D dC155L dC622L Min 6.2 3 0 48 48 Typ 7.2 4 0.8 50 50 Max 8.2 5 1.6 52 52 Units ns ns ns % %
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i
(19.44MHz)
VT-CMOS
tC19D
C19o VT-CMOS
(19.44MHz)
tC155D
C155o VT-CML
(155.52MHz)
tC622D
C622oA (622.08MHz) VT-LVPECL
Figure 14 - C19i Input to C19o, C155o and C622o Output Timing
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AC Electrical Characteristics- C622 Clocks Output Timing Characteristics 1 2 3 C622oA to C622oB C622oA to C622oC C622oA to C622oD Sym tC622D-AB tC622D-AC tC622D-AD Min -50 -50 -50 Typ 0 0 0 Max +50 +50 +50 Units ps ps ps
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions Typical figures are for design aid only: not guaranteed and not subject to production testing.
C622oA
VT-LVPECL
tC622D-AB
C622oB VT-LVPECL
tC622D-AC
C622oC VT-LVPECL
tC622D-AD
C622oD VT-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 15 - C622oB, C622oC, C622oD Outputs Timing
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Performance Characteristics - Functional (VCC = 3.3V 10%; TA = -40 to 85C ) Characteristics 1 Pull-in range Min 1000 Typ Max Units ppm
Data Sheet
Notes At nominal input reference frequency C19i = 19.44 MHz
2
Lock Time
300
ms
TA = -40 to 85C )
Performance Characteristics : Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3V 10%; ZL30414 Jitter Generation Performance Typ 0.52 0.58 0.34 Max 7.31 0.94 7.32 0.83 4.37 0.60
GR-253-CORE Jitter Generation Requirements Jitter Measurement Filter 50 kHz - 80 MHz
Equivalent limit in time domain
Interface (Category II) 1 OC-192 STS-192 OC-48 STS-48 OC-12 STS-12
Limit in UI 0.1 UIPP 0.01 UIRMS 0.1 UIPP 0.01 UIRMS 0.1 UIPP 0.01 UIRMS
Units psP-P psRMS psP-P psRMS psP-P psRMS
10.0 1.0 40.2 4.02 161 16.1
2
12 kHz - 20 MHz
3
12 kHz - 5 MHz
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
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10%; TA = -40 to 85C )
Data Sheet
Performance Characteristics : Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3V ZL30414 Jitter Generation Performance
Equivalent limit in time domain
G.813 Jitter Generation Requirements Jitter Measurement Filter Option 1 1 STM-64 4 MHz to 80 MHz 0.1 UIpp 10.0 -
Interface
Limit in UI
Typ
Max
Units
6.95 0.89 11.5 1.04 6.40 0.68 8.67 1.06 3.33 0.42 19.1 2.88
psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
0.49 20 kHz to 80 MHz 0.5 UIpp 50.2 0.82 2 STM-16 1 MHz to 20 MHz 0.1 UIpp 40.2 0.50 5 kHz to 20 MHz 0.5 UIpp 201 0.68 3 STM-4 250 kHz to 5 MHz 0.1 UIpp 161 0.26 1 kHz to 5 MHz 0.5 UIpp 804 1.51 Option 2 5 STM-64 4 MHz to 80 MHz 0.1 UIpp 10.0 0.49 20 kHz to 80 MHz 0.3 UIpp 30.1 0.82 6 STM-16 12 kHz - 20 MHz 0.1 UIpp 40.2 0.58 7 STM-4 12 kHz - 5 MHz 0.1 UIpp 161 0.34
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
6.95 0.89 11.5 1.04 7.32 0.83 4.37 0.60
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ZL30414
10%; TA = -40 to 85C )
Data Sheet
Performance Characteristics : Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3V ZL30414 Jitter Generation Performance Typ 0.50 5 kHz to 20 MHz 0.5UIpp 201 0.68 2 STM-4 250 kHz to 5 MHz 0.1 UIpp 161 0.26 1 kHz to 5 MHz 0.5 UIpp 804 1.51
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
EN 300 462-7-1 Jitter Generation Requirements Jitter Measurement Filter 1 MHz to 20 MHz
Equivalent limit in time domain
Interface 1 STM-16
Limit in UI 0.1 UIpp
Max 6.40 0.68 8.67 1.06 3.33 0.42 19.1 2.88
Units psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
40.2
21
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